This application claims priority to European Application Serial No. 01402956.5 filed Nov. 15, 2001. U.S. patent application Ser. No. 09/932,651 is incorporated herein by reference.
This invention generally relates to microprocessors, and more specifically to improvements in operation and use of cache memory, systems, and methods of making.
Microprocessors are general-purpose processors that provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever-increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general-purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general-purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
While, formerly, computer systems operated on a single application at one time, computer systems of today generally have several applications loaded into their main memories. The scheduling of multiple applications, running in parallel for the user, is managed by an operating system (OS). Most modern operating systems are designed with the concept of a virtual environment. Addresses coming from the processor are virtual addresses that map to actual (xe2x80x9cphysicalxe2x80x9d) addresses in main memory.
For these multi-tasking systems, an important constraint is the context switch. The context switch corresponds to the necessary sequence of actions that the OS needs to execute in order to accommodate several independent tasks on a single processor. The context switch is a limiting factor on the performance in systems with strong real-time requirements, because it takes a significant time and number of instructions to realize the context switch.
Multitasking systems in a virtual environment must deal with xe2x80x9caliasingxe2x80x9d of data which can occur when two or more different tasks cache data associated with the same physical address at two or more respective locations in the cache in accordance with the different virtual addresses used by the various tasks. When one task changes the value associated with a cached data item, that change will not be reflected in the cache locations of other virtual addresses that point to the same physical memory address. As part of a context switch, the operating system must invalidate the content of the cache so that other tasks will see the new value.
It is also beneficial to clean the cache, or a portion of the cache, in order to load in a new task in order to minimize processing delay due to xe2x80x9cmissxe2x80x9d processing.
The cleaning function associated with invalidating the cache can be very time consuming. Further, the cleaning function may be interrupted only at discrete time intervals, depending upon the cache cleaning design. For many applications that have tight real-time constraints, it is important that interrupts be allowed frequently. However, cleaning routines that have capacity to allow interrupts at frequent intervals often are the least efficient in completing the cleaning operation.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first embodiment of the invention, a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction can be executed in a sequence of instructions in accordance with a program counter. If an interrupt is received during execution of the clean instruction, execution of the clean instruction is suspended before it is completed. After performing a context switch, the interrupt is serviced. Upon returning from the interrupt service routine, execution of the clean instruction is resumed by comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction. If the same, execution of the clean instruction is resumed using the current content of the start register and end register. If different, execution of the clean instruction is restarted by storing the start parameter provided by clean instruction in the start register and by storing the end parameter in the end register. In this manner, no additional context information needs to be saved during a context switch in order to allow the clean instruction to be interruptible.
In another embodiment of the invention, an interruptible instruction is provided that performs a sequence of operations other than a cleaning operation.
In another embodiment of the invention, an interruptible instruction is provided that is also re-entrant. During service of the interrupt, another sequence of instructions is executed that contain another copy of the interruptible instruction. In this event, a second copy of the interruptible instruction is executed while execution of a first copy of the interruptible instruction is suspended.
Another embodiment of the invention is a digital system, such as a personal digital assistant, that provides such an interruptible instruction.